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FEATURES
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LTC2360/LTC2361/LTC2362 100ksps/250ksps/500ksps, 12-Bit Serial ADCs in TSOT-23 DESCRIPTION
The LTC(R)2360/LTC2361/LTC2362 are 100ksps/250ksps/ 500ksps, 12-bit, sampling A/D converters that draw only 0.5mA, 0.75mA and 1.1mA, respectively, from a single 3V supply. The supply current drops at lower sampling rates because these devices automatically power down after conversions. The full-scale input of the LTC2360/ LTC2361/LTC2362 is 0V to VDD or VREF. These ADCs are available in tiny 6- and 8-lead TSOT-23 packages. The serial interface, tiny TSOT-23 package and extremely high sample rate-to-power ratio make the LTC2360/ LTC2361/LTC2362 ideal for compact, low power, high speed systems. The high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
12-Bit Resolution Low Noise: 73dB SNR Low Power Dissipation: 1.5mW @ 100ksps 100ksps/250ksps/500ksps Sampling Rates Single Supply 2.35V to 3.6V Operation No Data Latency Sleep Mode with 0.1A Typical Supply Current Dedicated External Reference (TSOT23-8) 1V to 3.6V Digital Output Supply (TSOT23-8) SPI/MICROWIRETM Compatible Serial I/O Guaranteed Operation from -40C to 125C Tiny 6- and 8-Lead TSOT-23 Packages
APPLICATIONS
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Communication Systems Data Acquisition Systems Handheld Portable Devices Uninterrupted Power Supplies Battery-Operated Systems Automotive
TYPICAL APPLICATION
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE Part Number 3Msps LTC2366 1Msps LTC2365 500ksps LTC2362 250ksps LTC2361 100ksps LTC2360
Single 3V Supply, 500ksps, 12-Bit Sampling ADC
1200 3V SUPPLY CURRENT (A) 2.2F LTC2362 VDD VREF GND ANALOG INPUT 0V TO 3V AIN CONV SCK SDO OVDD DIGITAL OUTPUT SUPPLY 1V TO 3.6V 2.2F
236012 TA01a
Supply Current vs Sample Rate
VDD = 3.6V TA = 25C
1000 800 LTC2361 600 LTC2362 400 LTC2360 200 0
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTORS
1
10 100 SAMPLE RATE (ksps)
1000
236012 TA01b
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LTC2360/LTC2361/LTC2362 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD, OVDD)........................................4V VREF and Analog Input Voltage (Note 3).........................................-0.3V to (VDD + 0.3V) Digital Input Voltage......................-0.3V to (VDD + 0.3V) Digital Output Voltage ...................-0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW
Operating Temperature Range LTC2360C/LTC2361C/LTC2362C .............. 0C to 70C LTC2360I/LTC2361I/LTC2362I.............. -40C to 85C LTC2360H/LTC2361H/LTC2362H (Note 12).. -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
PIN CONFIGURATION
TOP VIEW VDD 1 VREF 2 GND 3 AIN 4 8 CONV 7 SCK 6 SDO 5 OVDD VDD 1 GND 2 AIN 3 TOP VIEW 6 CONV 5 SDO 4 SCK
TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 250C/W
S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 250C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC2362CTS8#TRMPBF LTC2362ITS8#TRMPBF LTC2362HTS8#TRMPBF LTC2362CS6#TRMPBF LTC2362IS6#TRMPBF LTC2362HS6#TRMPBF LTC2361CTS8#TRMPBF LTC2361ITS8#TRMPBF LTC2361HTS8#TRMPBF LTC2361CS6#TRMPBF LTC2361IS6#TRMPBF LTC2361HS6#TRMPBF LTC2360CTS8#TRMPBF LTC2360ITS8#TRMPBF LTC2360HTS8#TRMPBF LTC2360CS6#TRMPBF LTC2360IS6#TRMPBF TAPE AND REEL LTC2362CTS8#TRPBF LTC2362ITS8#TRPBF LTC2362HTS8#TRPBF LTC2362CS6#TRPBF LTC2362IS6#TRPBF LTC2362HS6#TRPBF LTC2361CTS8#TRPBF LTC2361ITS8#TRPBF LTC2361HTS8#TRPBF LTC2361CS6#TRPBF LTC2361IS6#TRPBF LTC2361HS6#TRPBF LTC2360CTS8#TRPBF LTC2360ITS8#TRPBF LTC2360HTS8#TRPBF LTC2360CS6#TRPBF LTC2360IS6#TRPBF PART MARKING* LTDBV LTDBV LTDBV LTDGP LTDGP LTDGP LTDGM LTDGM LTDGM LTDGN LTDGN LTDGN LTDGJ LTDGJ LTDGJ LTDGK LTDGK PACKAGE DESCRIPTION 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 6-Lead Plastic TSOT23 6-Lead Plastic TSOT23 6-Lead Plastic TSOT23 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 6-Lead Plastic TSOT23 6-Lead Plastic TSOT23 6-Lead Plastic TSOT23 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 8-Lead Plastic TSOT23 6-Lead Plastic TSOT23 6-Lead Plastic TSOT23 TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C
LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTDGK 6-Lead Plastic TSOT23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2360/LTC2361/LTC2362 CONVERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Gain Error Total Unadjusted Error (Notes 5, 6) (Note 6) (Note 7) (Note 6) (Note 6) (Note 6)
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l l
MIN 12
TYP 0.25 0.25 0.25 1 0.1 1.1
MAX 1 1 3.5 2 3.5
UNITS Bits LSB LSB LSBRMS LSB LSB LSB
ANALOG INPUT
SYMBOL VIN IIN CIN VREF IREF CREF tAP tJITTER PARAMETER Analog Input Voltage
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS S6 Package TS8 Package CONV = High Between Conversions During Conversions TS8 Package TS8 Package TS8 Package
l l l l l
MIN -0.05 -0.05
TYP
MAX VDD + 0.05 VREF + 0.05 1
UNITS V A pF pF
Analog Input Leakage Current Analog Input Capacitance Reference Input Voltage Reference Input Leakage Current Reference Input Capacitance Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter
20 4 1.4 20 1 0.3 VDD + 0.05 1
V A pF ns ns
DYNAMIC ACCURACY
SYMBOL SINAD SNR THD SFDR IMD PARAMETER
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 fIN1 = 97kHz, fIN2 = 100kHz for LTC2362 fIN1 = 47kHz, fIN2 = 49kHz for LTC2360/LTC2361 at 3dB at 0.1dB SINAD 68dB MIN TYP 72 73 -85 86 -75 10 2 1 MAX UNITS dB dB dB dB dB MHz MHz MHz Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth
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LTC2360/LTC2361/LTC2362 DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL VIH VIL IIH IIL CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current VDD = 2.35V to 3.6V, ISOURCE = 200A VDD = 2.35V to 3.6V, ISINK = 200A CONV = VDD CONV = VDD VOUT = 0V VOUT = VDD
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS 2.7V < VDD 3.6V 2.35V VDD 2.7V 2.7V < VDD 3.6V 2.35V VDD 2.7V VIN = VDD VIN = 0V
l l l l l l
MIN 2 1.7
TYP
MAX
UNITS V V
0.8 0.7 2.5 -2.5 2 VDD - 0.2 0.2 3 4 -10 10
V V A A pF V V A pF mA mA
POWER REQUIREMENT
SYMBOL VDD OVDD IDD PARAMETER Supply Voltage Digital Output Supply Voltage Supply Current Operational Mode, LTC2362 Operational Mode, LTC2361 Operational Mode, LTC2360 Sleep Mode Sleep Mode Sleep Mode Power Dissipation Operational Mode, LTC2362 Operational Mode, LTC2361 Operational Mode, LTC2360 Sleep Mode Sleep Mode Sleep Mode
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l
MIN 2.35 1.0V
TYP 3.0
MAX 3.6 3.6
UNITS V V mA mA mA A A A mW mW mW W W W
fSMPL = 500ksps fSMPL = 250ksps fSMPL = 100ksps 0C to 70C -40C to 85C -40C to 125C fSMPL = 500ksps fSMPL = 250ksps fSMPL = 100ksps 0C to 70C -40C to 85C -40C to 125C
l l l l l l l l l l l l
1.1 0.75 0.5 0.1 0.1 0.1 3.3 2.25 1.5 0.3 0.3 0.3
2 1.5 1 2 2 5 7.2 5.4 3.6 7.2 7.2 18
PD
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LTC2360/LTC2361/LTC2362 TIMING CHARACTERISTICS
SYMBOL fSMPL(MAX) fSCK tSCK tACQ tCONV t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER Maximum Sampling Frequency Shift Clock Frequency Shift Clock Period Acquisition Time Conversion Time Minimum Positive CONV Pulse Width SCK Setup Time After CONV SDO Enabled Time After CONV SCK Low Time SCK High Time SDO Data Valid Hold Time After SCK SDO Into Hi-Z State Time After CONV (Note 8) (Note 8) (Notes 8, 9) (Note 11) (Note 11) (Notes 8, 9)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
LTC2360 CONDITIONS (Notes 8, 9) (Notes 8, 9)
l l l l l l l l l l l
LTC2361 MAX 10 MIN 250 25 40 10 4 1 3 3 16 16 8 16 8 40% 40% 4 40% 40% 4 6 0.5 1.5 1.5 16 20 TYP MAX MIN 500
LTC2362 TYP MAX 50 2 UNITS kHz MHz ns s s s s ns 16 8 ns ns tSCK tSCK ns 6 ns
MIN 100 100 2 8 8 16
TYP
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV
SDO Data Valid Access Time After SCK (Notes 8, 9, 10) l 40% 40% 4 6
(Notes 8, 9, 10) l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When pins AIN and VREF are taken below GND or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below GND or above VDD without latch-up. Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise specified. Note 5: Integral linearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 6: Linearity, offset and gain specifications apply for a single-ended AIN input with respect to GND. Note 7: Typical RMS noise at code transitions. Note 8: Guaranteed by characterization. All input signals are specified with tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V. Note 9: All timing specifications given are with a 10pF capacitance load. With a capacitance load greater than this value, a digital buffer or latch must be used. Note 10: The time required for the output to cross the VIH or VIL voltage. Note 11: Guaranteed by design, not subject to test. Note 12: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C.
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LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs Output Code
1 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G01
TA = 25C, VDD = OVDD = VREF (LTC2360, Note 4) Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package)
1 0.8 NONLINEARITY ERROR (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 MIN DNL MAX INL MIN INL MAX DNL VDD = 3.6V
Differential Nonlinearity vs Output Code
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G02
VDD = 3V
VDD = 3V
-1 0.8
1.2
1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V)
3.6
236012 G03
Histogram for 16384 Conversions
10000 VDD = 3V 8000 SUPPLY CURRENT (A) 400 500
Supply Current vs Sample Rate
20.0 VDD = 3.6V REFERENCE CURRENT (A) 16.0
Reference Current vs Sample Rate (TS8 Package)
VDD = 3.6V
COUNT
6000
300
12.0
4000
200
8.0
2000
100
4.0
0
0 2045 2046 2047 2048 CODE 2049 2050
236012 G04
0
10 20 30 40 50 60 70 80 90 100 SAMPLING FREQUENCY (ksps)
236012 G05
0.0
0
10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (ksps)
236012 G06
SINAD vs Input Frequency
74 VDD = 3.6V -80 73 VDD = 3.0V SINAD (dB) 72 VDD = 2.35V THD (dB) -82 -84 -86 -88 70 -90 -78
THD vs Input Frequency
0 -20 VDD = 2.35V -40 -60 -80
48kHz Sine Wave 8192 FFT Plot
VDD = 3V fSMPL = 100ksps
71
VDD = 3.6V
VDD = 3.0V 69 -92 1 10 INPUT FREQUENCY (kHz) 100
236012 G07
MAGNITUDE (dB)
-100 -120 -140
1
10 INPUT FREQUENCY (kHz)
100
236012 G08
0
10
30 20 40 INPUT FREQUENCY (kHz)
50
2306012 G09
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LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs Output Code
1 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G10
TA = 25C, VDD = OVDD = VREF (LTC2361, Note 4) Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package)
1 0.8 NONLINEARITY ERROR (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 MIN DNL MAX INL MIN INL MAX DNL VDD = 3.6V
Differential Nonlinearity vs Output Code
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G11
VDD = 3V
VDD = 3V
-1 0.8
1.2
1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V)
3.6
236012 G12
Histogram for 16384 Conversions
10000 VDD = 3V 8000 SUPPLY CURRENT (A) 800
Supply Current vs Sample Rate
50.0 VDD = 3.6V 600 REFERENCE CURRENT (A) 40.0
Reference Current vs Sample Rate (TS8 Package)
VDD = 3.6V
COUNT
6000
30.0
400
4000
20.0
200
2000
10.0
0
2045
2046
2047 2048 CODE
2049
2050
236012 G13
0
0
50
150 100 200 SAMPLE RATE (ksps)
250
236012 G14
0.0
0
50
150 200 100 SAMPLE RATE (ksps)
250
236012 G15
SINAD vs Input Frequency
74 VDD = 3.6V 73 -71 -73 -75
THD vs Input Frequency
0 -20 -40 -60 -80
124kHz Sine Wave 8192 FFT Plot
VDD = 3V fSMPL = 250ksps
SINAD (dB)
VDD = 2.35V 71
THD (dB)
72
VDD = 3.0V
-79 -81 -83 -85 VDD = 3.6V
VDD = 2.35V
70
-87 -89 -120 VDD = 3.0V 1 10 100 INPUT FREQUENCY (kHz) 1000
236012 G17
69
1
10 100 INPUT FREQUENCY (kHz)
1000
2306012 G16
-91
MAGNITUDE (dB)
-77
-100
-140
0
25
75 50 100 INPUT FREQUENCY (kHz)
125
2306012 G18
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LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs Output Code
1 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G19
TA = 25C, VDD = OVDD = VREF (LTC2362, Note 4) Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package)
1 0.8 NONLINEARITY ERROR (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 MIN DNL MAX INL MIN INL MAX DNL VDD = 3.6V
Differential Nonlinearity vs Output Code
1 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
236012 G20
VDD = 3V
VDD = 3V
-1 0.8
1.2
1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V)
3.6
236012 G21
Histogram for 16384 Conversions
10000 VDD = 3V 8000 SUPPLY CURRENT (A) 1000 1200
Supply Current vs Sample Rate
80.0 VDD = 3.6V REFERENCE CURRENT (A) 60.0
Reference Current vs Sample Rate (TS8 Package)
VDD = 3.6V
800 600 400 200 0
COUNT
6000
40.0
4000
2000
20.0
0
2045
2046
2047 2048 CODE
2049
2050
236012 G22
0
100
300 200 400 SAMPLE RATE (ksps)
500
236012 G23
0.0
0
50 100 150 200 250 300 350 400 450 500 SAMPLE RATE (ksps)
236012 G24
SINAD vs Input Frequency
74 VDD = 3.6V 73 VDD = 3.0V -71 -75 SINAD (dB) THD (dB) 72 VDD = 2.35V -79 -83 70 -87 -91 1 10 100 INPUT FREQUENCY (kHz) 1000
2306012 G25
THD vs Input Frequency
-67 0
248kHz Sine Wave 8192 FFT Plot
VDD = 3V -20 fSMPL = 500ksps -40 -60 -80
VDD = 2.35V
71
VDD = 3.0V
VDD = 3.6V
69
MAGNITUDE (dB)
-100 -120 -140
1
10 100 INPUT FREQUENCY (kHz)
1000
2306012 G26
0
50
150 100 200 INPUT FREQUENCY (kHz)
250
2306012 G27
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LTC2360/LTC2361/LTC2362 PIN FUNCTIONS
S6 Package VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to VDD. Bypass to GND and to a solid ground plane with a 2.2F ceramic capacitor (or 2.2F tantalum in parallel with 0.1F ceramic). GND (Pin 2): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 3): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VDD. SCK (Pin 4): Shift Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. SDO (Pin 5): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. CONV (Pin 6): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. TS8 Package VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2F ceramic capacitor (or 2.2F tantalum in parallel with 0.1F ceramic). VREF (Pin 2): Reference Input. VREF defines the input span of the ADC, 0V to VREF. The VREF range is 1.4V to VDD. Bypass to GND and to a solid ground plane with a 2.2F ceramic capacitor (or 2.2F tantalum in parallel with 0.1F ceramic). GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): Output Driver Supply for SDO. The OVDD range is 1V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2F ceramic capacitor (or 2.2F tantalum in parallel with 0.1F ceramic). OVDD can be driven separately from VDD and OVDD can be higher than VDD. SDO (Pin 6): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. SCK (Pin 7): Shift Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out.
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LTC2360/LTC2361/LTC2362 BLOCK DIAGRAM
2.2F 2.2F
1
VDD
ANALOG INPUT RANGE 0V TO VREF
AIN 4 S AND H 12-BIT ADC THREE-STATE SERIAL OUTPUT PORT SDO 6
VREF 2 2.2F 3 GND TIMING LOGIC SCK CONV 7 8
TS8 PACKAGE
236012 BD
TIMING DIAGRAMS
t8 CONV 1.6V SCK Hi-Z
236012 F01
1.6V VIH VIL
236012 F02
SDO
SDO
Figure 1. SDO Into Hi-Z State After CONV Rising Edge
Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t4 SCK 1.6V VIH VIL
236012 F03
SDO
Figure 3. SDO Data Valid Acess Time After SCK Falling Edge
10
+
5 OVDD t7
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LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
DC PERFORMANCE The noise of an ADC can be evaluated in two ways: signal-to-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2360/LTC2361/ LTC2362 excel in both. Figure 5 demonstrates that the LTC2360/LTC2361/LTC2362 have an SNR of over 73dB. The noise in the time domain histogram is the transition noise associated with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 4, the distribution of output codes is shown for a DC input that has been digitized 16384 times. The distribution is Gaussian and the RMS code transition is about 0.32LSB. This corresponds to a noise level of 73dB relative to a full scale of 3V.
10000 VDD = 3V 8000
DYNAMIC PERFORMANCE The LTC2360/LTC2361/LTC2362 have excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used to test the ADCs' frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADCs' spectral content can be examined for frequencies outside the fundamental. Figures 5 and 6 show typical LTC2361 and LTC2362 FFT plots respectively.
COUNT
6000
4000
2000
0
2045
2046
2047 2048 CODE
2049
2050
236012 F04
Figure 4. Histogram for 16384 Conversions
0 -20 -40 -60 -80 -100 -120 -140 VDD = 3V fSMPL = 250ksps fIN = 124kHz SINAD = 73dB THD = -84dB 0 -20 -40 -60 -80 -100 -120 -140 VDD = 3V fSMPL = 500ksps fIN = 248kHz SINAD = 73dB THD = -81dB
MAGNITUDE (dB)
0
25
75 50 100 INPUT FREQUENCY (kHz)
125
236012 F05
MAGNITUDE (dB)
0
50
150 100 200 INPUT FREQUENCY (kHz)
250
236012 F06
Figure 5. LTC2361 FFT Plot
Figure 6. LTC2362 FFT Plot
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LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
Signal-to-Noise plus Distortion Ratio The signal-to-noise plus distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 6 shows a typical FFT with a 500kHz sampling rate and a 248kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist frequency of 250kHz. Effective Number of Bits The effective number of bits (ENOB) is a measurement of the resolution of an ADC and is directly related to SINAD by the equation: ENOB = SINAD - 1.76 6.02 rate of 500kHz, the LTC2362 maintains ENOB above 11 bits up to the Nyquist input frequency of 250kHz (refer to Figure 7). Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20log V2 2 + V3 2 + V4 2 + ...Vn 2 V1
where ENOB is the effective number of bits of resolution and SINAD is expressed in dB. At the maximum sampling
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs. Input Frequency is shown in Figure 8. The LTC2362 has excellent distortion performance up to the Nyquist frequency and beyond.
74 VDD = 3.6V 73 72 SINAD (dB) 71 70 69 68 67 VDD = 2.35V VDD = 3.0V
12
-67 -71
11.67 THD (dB) ENOB
-75 -79 -83 -87 -91 VDD = 2.35V
11.34
VDD = 3.0V
VDD = 3.6V
11
1
10 100 INPUT FREQUENCY (kHz)
1000
2306012 F07
1
10 100 INPUT FREQUENCY (kHz)
1000
2306012 F08
Figure 7. LTC2362 ENOB and SINAD vs Input Frequency
Figure 8. LTC2362 THD vs Input Frequency
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12
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermoduation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD ( fa fb ) = 20log Amplitude at ( fa fb ) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of reconstructed fundamental is reduced by 3dB for full-scale input signal. The full-linear bandwidth is the input frequency at which the SINAD has dropped to 68dB (11 effective bits). The LTC2362 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies; SINAD becomes dominated by distortion at frequencies far beyond Nyquist.
0 -20 MAGNITUDE (dB) -40 -60 -80 VDD = 3.6V fSMPL = 500ksps fa = 99kHz fb = 101kHz IMD = -76.5dB
-100 -120
0
50
100 200 150 INPUT FREQUENCY (kHz)
250
236012 F09
Figure 9. LTC2362 Intermodulation Distortion Plot
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13
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
OVERVIEW The LTC2360/LTC2361/LTC2362 use a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. All devices operate from a single 2.35V to 3.6V supply. The conversion time of the devices is controlled by an internal oscillator, which allows the LTC2360/LTC2361/LTC2362 to sample at a rate of 100ksps, 250ksps and 500ksps respectively. The LTC2360/LTC2361/LTC2362 contain a 12-bit, switchedcapacitor ADC, a sample-and-hold, a serial interface(see Block Diagram) and are available in tiny 6- or 8-lead TSOT-23 packages. The S6 package of the LTC2360/LTC2361/LTC2362 uses VDD as the reference and has an analog input range of 0V to VDD. The ADC samples the analog input with respect to GND and outputs the result through the serial interface. The TS8 package provides two additional pins: a reference pin, VREF, and an output supply pin, OVDD. The ADC can operate with reduced spans down to 1.4V and achieve 342V resolution. OVDD controls the output swing of the digital output pin, SDO, and allows the device to communicate with 1.8V, 2.5V or 3V digital systems. SERIAL INTERFACE The LTC2360/LTC2361/LTC2362 communicate with microcontrollers, DSPs and other external circuitry via a 3-wire interface. Figure 10 shows the operating sequence of the serial interface. Data Transfer A rising CONV edge starts a conversion and disables SDO. After the conversion, the ADC automatically goes into sleep mode, drawing only leakage current. CONV going low enables SDO and clocks out the MSB bit, B11. SCK then synchronizes the data transfer with each bit being transmitted on the falling SCK edge and can be captured on the rising SCK edge. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely (see Figure 10). For example, 16-clocks at SCK will produce the 12-bit data and four trailing zeros on SDO. SLEEP MODE The LTC2360/LTC2361/LTC2362 enter sleep mode to save power after each conversion if CONV remains high. In sleep mode, all bias currents are shut down and only leakage currents remain (about 0.1A). The sample-and-hold is in hold mode while the ADC is in sleep mode. The ADC returns to sample mode after the falling edge of CONV during power-up (see Figure 10). Exiting Sleep Mode and Power-Up Time By taking CONV low, the ADC powers up and acquires an input signal completely after the aquisition time (tACQ). After tACQ, the ADC can perform a conversion as described in the Serial Interface section (see Figure 10).
CONV tCONV SCK SLEEP MODE t2
BY TAKING CONV LOW, THE DEVICE POWERS UP AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ t6 1 t3 B11 (MSB) t1 tTHROUGHPUT *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY tACQ 2 t4 B10 B9 3 4 t5 B3 9 10 t7 B2 B1 B0*
236012 F10
RECOMMENDED HIGH OR LOW Hi-Z STATE
11
12 t8
SDO
Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram
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14
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 0.5mA, 0.75mA and 1.1mA for the LTC2360/LTC2361/LTC2362 and automatically entering sleep mode right after a conversion, these devices achieve extremely low power consumption over a wide range of sample rates (see Figure 11). The sleep mode allows the supply current to drop with reduced sample rate. Several things must be taken into account to achieve such low power consumption. Minimize Power Consumption in Sleep Mode The LTC2360/LTC2361/LTC2362 enter sleep mode after each conversion if CONV remains high and draw only leakage current (see Figure 10). If the CONV input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CONV pin to GND when it is low and to VDD when it is high. After the conversion with CONV staying high, the converter is in sleep mode and draws only leakage current. The status of the SCK input has no effect on supply current during this time. For the best performance, hold SCK either high or low while the ADC is converting. Minimize the Device Active Time In systems that have significant time between conversions, the ADC draws a minimal amount of power. Figures 12 and 13 show two ways to minimize the amount of time the ADC draws power. In Figure 12, the ADC draws power during tACQ and tCONV and is in sleep mode for the rest of the time. The conversion results are available at the next CONV falling edge. In Figure 13, the ADC draws twice the power than that in Figure 12, but the conversion results are available during tDATA. The user can use the fastest SCK available in the system to shorten data transfer time, tDATA as long as t4 and t7 are not violated. SDO Loading
800 LTC2361 600 LTC2362 400 LTC2360 200 0
1200 1000 SUPPLY CURRENT (A)
VDD = OVDD = VREF = 3.6V TA = 25C
1
10 100 SAMPLE RATE (ksps)
1000
236012 TA01b
Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the SDO pin can add more than 50A to the supply current at a 200kHz clock frequency. An extra 50A or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C * V * f currents must be evaluated with the troublesome ones minimized.
Figure 11. Supply Current vs Sample Rate
CONV
SAMPLING INPUT AND TRANSFERRING DATA tACQ
EXECUTING A CONVERSION AND PUTTING THE DEVICE INTO SLEEP MODE
tCONV
SLEEP MODE RECOMMENDED HIGH OR LOW
SCK 1 SDO B11 2 B10 3 B9 4 9 B3 10 B2 11 B1 12 B0
Hi-Z STATE tTHROUGHPUT = tACQ + tCONV + tSLEEPMODE
236012 F12
Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up
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15
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
CONV ACQUIRE INPUT tACQ SCK tCONV RECOMMENDED HIGH OR LOW 1 SDO B11 2 B10 3 B9 4 9 B3 10 B2 11 B1 12 B0 Hi-Z STATE
236012 F13
EXECUTE CONVERSION DATA TRANSFER
EXECUTING A DUMMY CONVERSION AND PUT THE DEVICE INTO SLEEP MODE
tDATA
tCONV
SLEEP MODE RECOMMENDED HIGH OR LOW
tTHROUGHPUT = tACQ + 2 * tCONV + tDATA + tSLEEPMODE
Figure 13. Minimize the Time When the Device Draws Power, While the Conversion Results are Available Right After Conversion
SINGLE-ENDED ANALOG INPUT Driving the Analog Input The analog input of the LTC2360/LTC2361/LTC2362 is easy to drive. The input draws only one small current spike while charging the sample-and-hold capacitor with the ADC going into track mode. During the conversion, the analog input draws only a small leakage current. If the source impedance of the driving circuit is low, then the input of the LTC2360/LTC2361/LTC2362 can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts (settling time must be less than tACQ for full throughput rate). While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 10MHz, then the output impedance at 10MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 8MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are
used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2360/LTC2361/LTC2362 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2360/LTC2361/LTC2362. (More detailed information is available on the Linear Technology website at www.linear.com.) LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. LT(R)1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to 15V supplies. Very high AVOL, 500V offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are -93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LTC6241: Dual 18MHz, Low Noise, Rail-to-Rail, CMOS Voltage FB Amplifier. 2.8V to 6V supplies. Very high AVOL and 125V offset. It is suitable for applications with a single 5V supply. Quad version is available as LTC6242. LT1797: Unity-Gain Stable 10MHz, Rail-to-Rail Voltage Feedback Amplifier. LT1801: 180MHz GBWP -75dBc at 500kHz, 2mA/Ampli, fier, 8.5nV/Hz. LT6203: 100MHz GBWP -80dBc Distortion at 1MHz, Unity, Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/Hz.
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16
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
Input Filtering and Source Impedance The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2360/LTC2361/LTC2362 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 10MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 14 shows a 220pF capacitor from AIN to ground and a 51 source resistor to limit the input bandwidth to 10MHz. The 220pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with the 20pF of input capacitance, will reduce the rated 10MHz bandwidth and increase acquisition time beyond 500ns. Reference Input On the TS8 package of the LTC2360/LTC2361/LTC2362, the voltage on the VREF pin defines the full-scale range of the ADC. The reference voltage can range from VDD down to 1.4V. Input Range The analog input of the LTC2360/LTC2361/LTC2362 is driven single-ended with respect to GND from a single supply. The input may swing up to VDD for the S6 package and to VREF for the TS8 package. The 0V to 2.5V range is also ideally suited for single-ended input use with VDD or VREF = 2.5V for single supply applications. If the difference between the AIN input and GND exceeds VDD for the S6 package or VREF for the TS8 package, the output code will stay fixed at all ones, and if this difference goes below 0V, the output code will stay fixed at all zeros. Figure 15 shows the ideal input/output characteristics for the LTC2360/LTC2361/LTC2362. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ..., FS - 1.5LSB). The output code is straight binary with 1LSB = VDD/4096 for the S6 package and 1LSB = VREF /4096 for the TS8 package.
111...111 111...110 UNIPOLAR OUTPUT CODE 000...001 000...000 0 1LSB INPUT VOLTAGE (V) FS - 1LSB
236012 F15
LTC2362 1 2.2F 220pF 51 2 3 VDD GND AIN CONV SDO SCK 6 5 4
236012 F14
Figure 14. RC Input Filter
Figure 15. Transfer Characteristics
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17
LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION
BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC2360/LTC2361/LTC2362, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by the ground plane. High quality tantalum and ceramic bypass capacitors should be used at the VDD pin as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 2.2F surface mount AVX capacitor with a 0.1F ceramic is recommended for the VDD and VREF pins. Alternatively, 2.2F ceramic chip capacitors such as Murata GRM235Y5V106Z016 may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Figure 16 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC2360/LTC2361/LTC2362. The ground return from the LTC2360/LTC2361/LTC2362 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the ADC data bus.
+
CVDD 2.2F
PIN 1 CAIN
VDD GND AIN
CONV SDO SCK
VIAS TO GROUND PLANE
236012 F16
Figure 16. Power Supply Ground Practice
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18
LTC2360/LTC2361/LTC2362 PACKAGE DESCRIPTION
S6 Package 6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62 MAX 0.95 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC 0.80 - 0.90
0.30 - 0.45 6 PLCS (NOTE 3)
0.20 BSC 1.00 MAX DATUM `A'
0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING
0.09 - 0.20 (NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
TS8 Package 8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.52 MAX 0.65 REF 2.90 BSC (NOTE 4)
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.65 BSC 0.80 - 0.90
0.22 - 0.36 8 PLCS (NOTE 3)
0.20 BSC 1.00 MAX DATUM `A'
0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING
0.09 - 0.20 (NOTE 3)
1.95 BSC
TS8 TSOT-23 0802
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
236012f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2360/LTC2361/LTC2362 TYPICAL APPLICATION
Recommended AC Test Circuitry for the LTC2362
3V + 4.7F 1k 1% 1.5V AC INPUT 4.7F 50 5% AIN 220pF 2200pF 1k 1% GND
236012 TA02
+ 2.2F VDD CONV LTC2362 SCK SDO TO MCU
RELATED PARTS
PART NUMBER ADCs LTC1403/LTC1403A LTC1407/LTC1407A LTC1860 LTC1860L LTC1861 LTC1861L LTC1863 LTC1863L LTC1864/LTC1865 LTC1867 LTC1867L LTC2355/LTC2356 LTC2365/LTC2366 DACs LTC1592 LTC2630 References LT1460-2.5 LT1461-2.5 LT1790-2.5 LT6660 Micropower Series Voltage Reference Precision Voltage Reference Micropower Series Reference in SOT-23 Ultra-Tiny Micropower Series Reference 0.1% Initial Accuracy, 10ppm Drift 0.05% Initial Accuracy, 3ppm Drift 0.05% Initial Accuracy, 10ppm Drift 2mm x 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift
236012f
DESCRIPTION 12-/14-Bit, 2.8Msps Serial Sampling ADC 12-/14-Bit, 3Msps Simultaneous Sampling ADC 12-Bit, 250ksps Serial ADC 12-Bit, 150ksps Serial ADC 12-Bit, 250ksps Serial ADC 12-Bit, 150ksps Serial ADC 12-Bit, 200ksps Serial ADC 8-Channel ADC 12-Bit, 250ksps Serial ADC 8-Channel ADC 16-Bit, 250ksps Serial ADC 16-Bit, 200ksps Serial ADC 8-Channel ADC 16-Bit, 175ksps Serial ADC 8-Channel ADC 12-/14-Bit, 3.5Msps Serial ADCs 12-Bit, 1/3 Msps Serial ADCs in TSOT23
COMMENTS 3V, Differential Input, 12mW, MSOP Package 3V, 2-Channel Differential, 14mW, MSOP Package 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 3.3V Supply, Differential Input, 18mW, MSOP Package 2.35V to 3.6V Supply, Pin and Software Compatible to LTC2360/LTC2361/LTC2362 1LSB INL/DNL, Software Selectable Spans 87dB SFDR, 20ns Settling Time SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)
16-Bit, Serial SoftSpanTM IOUT DAC 12-/10-/8-Bit Single VOUT DACs
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs
SoftSpan is a trademark of Linear Technology Corporation.
20 Linear Technology Corporation
(408) 432-1900
LT 0408 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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